EDA MCP Server for Yosys, Icarus, OpenLane
Enable AI-driven Verilog synthesis, simulation, and ASIC flows using an MCP server with Yosys, Icarus, OpenLane, GTKWave, and KLayout
npx -y @NellyW8/mcp-EDAOverview
This project provides an MCP (Model Context Protocol) server that exposes common open-source EDA tools — Yosys, Icarus Verilog, OpenLane, GTKWave and KLayout — as programmatic services. The server is intended to be used by AI agents or other automation layers that need to run synthesis, simulation, or ASIC flows and retrieve files, logs, and artifacts in a structured way. Using MCP lets an LLM or assistant call into real EDA tools as part of a larger developer workflow, without manual shell access.
The server typically runs next to your toolchain (or in a container) and manages invocation, file staging, artifact collection, and simple sandboxing. That makes it useful for automated verification loops, reproducible flow runs, and interactive AI-assisted design work where a model issues commands like “synthesize this Verilog” or “run the OpenLane full flow and return GDS.” The server returns standard outputs (stdout/stderr), produced files (netlists, VCD/GHW, GDS), and structured status so the caller can reason about next steps.
Features
- Exposes Yosys for RTL synthesis and netlist extraction
- Runs Icarus Verilog (iverilog + vvp) for simulation and waveform generation
- Orchestrates OpenLane ASIC flows (synthesize, place & route, LVS/DRC) and provides GDS/artifacts
- Produces GTKWave/gtkwave-compatible waveforms and metadata for browsing
- Launches KLayout or prepares files for layout inspection
- File staging: upload inputs and download generated artifacts
- Structured responses: status, logs, and artifact URLs or bundled archives
- Optional Docker/container-friendly deployment for reproducible environments
- Basic sandboxing and resource limits to isolate tool runs
Installation / Configuration
Two common deployment patterns: local Python environment or Docker. Clone the repo and follow one of the examples below.
Clone the repository:
Python virtualenv install (example):
# Start the MCP server (replace with actual entrypoint if different)
Example config.yaml
server:
host: 0.0.0.0
port: 9999
tools:
yosys:
path: /usr/bin/yosys
timeout: 120
iverilog:
path: /usr/bin/iverilog
openlane:
path: /opt/openlane
run_timeout: 7200
artifacts_dir: /var/lib/mcp-eda/artifacts
allow_remote_uploads: true
Docker Compose example
version: "3.8"
services:
mcp-eda:
image: nellyw8/mcp-eda:latest
container_name: mcp-eda
ports:
- "9999:9999"
volumes:
- ./artifacts:/var/lib/mcp-eda/artifacts
- /opt/openlane:/opt/openlane:ro
- /usr/local/bin/yosys:/usr/bin/yosys:ro
environment:
- MCP_CONFIG=/etc/mcp-eda/config.yaml
Start with:
Configuration tips
- Point tool paths to the installed binaries or mount tool installations into containers.
- Tune timeouts and memory limits to protect the host.
- Use a dedicated artifacts directory with controlled permissions.
Available Resources
| Tool | Purpose | Notes |
|---|---|---|
| Yosys | RTL synthesis, netlist generation | Supports generating BLIF/EDIF/Verilog netlists |
| Icarus Verilog | Compile & run Verilog tests, produce VCD/GHW | Generate waveforms compatible with GTKWave |
| OpenLane | End-to-end ASIC flow (synthesis→P&R→GDS) | Long-running; expect large disk usage |
| GTKWave | Waveform viewing |